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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Product Preview
MC54/74HC390A
J SUFFIX CERAMIC PACKAGE CASE 620-10
1
Dual 4-Stage Binary Ripple Counter with / 2 and / 5 Sections
High-Performance Silicon-Gate CMOS
The MC54/74HC390A is identical in pinout to the LS390. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. This device consists of two independent 4-bit counters, each composed of a divide-by-two and a divide-by-five section. The divide-by-two and divide-by-five counters have separate clock inputs, and can be cascaded to implement various combinations of / 2 and/or / 5 up to a / 100 counter. Flip-flops internal to the counters are triggered by high-to-low transitions of the clock input. A separate, asynchronous reset is provided for each 4-bit counter. State changes of the Q outputs do not occur simultaneously because of internal ripple delays. Therefore, decoded output signals are subject to decoding spikes and should not be used as clocks or strobes except when gated with the Clock of the HC390A. * * * * * * Output Drive Capability: 10 LSTTL Loads Outputs Directly Interface to CMOS, NMOS, and TTL Operating Voltage Range: 2 to 6 V Low Input Current: 1 A High Noise Immunity Characteristic of CMOS Devices In Compliance with the Requirements Defined by JEDEC Standard No 7A * Chip Complexity: 244 FETs or 61 Equivalent Gates
16
16 1
N SUFFIX PLASTIC PACKAGE CASE 648-08
16 1
D SUFFIX SOIC PACKAGE CASE 751B-05 DT SUFFIX TSSOP PACKAGE CASE 948F-01
16 1
ORDERING INFORMATION MC54HCXXXAJ MC74HCXXXAN MC74HCXXXAD MC74HCXXXADT Ceramic Plastic SOIC TSSOP
PIN ASSIGNMENT
CLOCK Aa 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VCC CLOCK Ab RESET b QAb CLOCK Bb QBb QCb QDb
LOGIC DIAGRAM
RESET a QAa CLOCK Ba
CLOCK A
1, 15
/2 COUNTER
3, 13
QA
QBa QCa QDa GND
5, 11 CLOCK B 4, 12 /5 COUNTER
QB 6, 10 QC 7, 9 QD A X
FUNCTION TABLE
Clock B X X X Reset H L L Action Reset / 2 and / 5 Increment /2 Increment /5
RESET
2, 14 PIN 16 = VCC PIN 8 = GND
This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice.
10/95
(c) Motorola, Inc. 1995
1
REV 0
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* Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. Derating -- Plastic DIP: - 10 mW/_C from 65_ to 125_C Ceramic DIP: - 10 mW/_C from 100_ to 125_C SOIC Package: - 7 mW/_C from 65_ to 125_C TSSOP Package: - 6.1 mW/_C from 65_ to 125_C For high frequency or heavy load considerations, see Chapter 2 of the Motorola High-Speed CMOS Data Book (DL129/D).
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MAXIMUM RATINGS*
MOTOROLA
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
RECOMMENDED OPERATING CONDITIONS
MC54/74HC390A
Symbol
Vin, Vout
Symbol
Symbol
VCC
Vout
Tstg
ICC
Iout
VCC
Vin
PD
TL
VOH
tr, tf
Iin
TA
VIH
VIL
Lead Temperature, 1 mm from Case for 10 Seconds Plastic DIP, SOIC or TSSOP Package (Ceramic DIP)
Storage Temperature
Power Dissipation in Still Air, Plastic or Ceramic DIP SOIC Package TSSOP Package
DC Supply Current, VCC and GND Pins
DC Output Current, per Pin
DC Input Current, per Pin
DC Output Voltage (Referenced to GND)
DC Input Voltage (Referenced to GND)
DC Supply Voltage (Referenced to GND)
Input Rise and Fall Time (Figure 1)
Operating Temperature, All Package Types
DC Input Voltage, Output Voltage (Referenced to GND)
DC Supply Voltage (Referenced to GND)
Minimum High-Level Output Voltage
Maximum Low-Level Input Voltage
Minimum High-Level Input Voltage
Parameter
Parameter
Parameter
Vin = VIH or VIL |Iout| 20 A
Vin = VIH or VIL |Iout| |Iout| |Iout|
Vout = 0.1 V or VCC - 0.1 V |Iout| 20 A
Vout = 0.1 V or VCC - 0.1 V |Iout| 20 A
v
v
v
VCC = 2.0 V VCC = 3.0 V VCC = 4.5 V VCC = 6.0 V
Test Conditions
- 0.5 to VCC + 0.5
- 0.5 to VCC + 0.5
- 65 to + 150
- 0.5 to + 7.0
2 - 55 Min 2.0 Value
v 2.4 mA v 4.0 mA v 5.2 mA
0 0 0 0
0
50
25
20
260 300
750 500 450
+ 125
1000 600 500 400
VCC
Max
6.0
VCC V
3.0 4.5 6.0
2.0 4.5 6.0
2.0 3.0 4.5 6.0
2.0 3.0 4.5 6.0
Unit
Unit
mW
mA
mA
mA
_C
_C
_C
ns
V
V
V
V
V
- 55 to 25_C
0.5 0.9 1.35 1.8
1.5 2.1 3.15 4.2
2.48 3.98 5.48
1.9 4.4 5.9
This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, Vin and Vout should be constrained to the range GND (Vin or Vout) VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open.
Guaranteed Limit
v 85_C v 125_C
High-Speed CMOS Logic Data DL129 -- Rev 6 0.5 0.9 1.35 1.8 1.5 2.1 3.15 4.2 2.34 3.84 5.34 1.9 4.4 5.9
v
0.5 0.9 1.35 1.8
1.5 2.1 3.15 4.2
2.20 3.70 5.20 1.9 4.4 5.9
v
Unit
V V V
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NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High-Speed CMOS Data Book (DL129/D).
High-Speed CMOS Logic Data DL129 -- Rev 6 Symbol Symbol tPLH, tPHL tPLH, tPHL tPLH, tPHL tPLH, tPHL tPLH, tPHL VOL tPHL fmax ICC Iin Maximum Quiescent Supply Current (per Package) Maximum Input Leakage Current Maximum Low-Level Output Voltage Maximum Propagation Delay, Reset to any Q (Figures 2 and 3) Maximum Propagation Delay, Clock B to QD (Figures 1 and 3) Maximum Propagation Delay, Clock B to QC (Figures 1 and 3) Maximum Propagation Delay, Clock B to QB (Figures 1 and 3) Maximum Propagation Delay, Clock A to QC (QA connected to Clock B) (Figures 1 and 3) Maximum Propagation Delay, Clock A to QA (Figures 1 and 3) Maximum Clock Frequency (50% Duty Cycle) (Figures 1 and 3) Parameter Parameter Vin = VIH or VIL |Iout| 20 A Vin = VCC or GND Iout = 0 A Vin = VCC or GND
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tf = tf = 6 ns)
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Vin = VIH or VIL |Iout| |Iout| |Iout|
v
Test Conditions
3
v 2.4 mA v 4.0 mA v 5.2 mA
VCC V
VCC V
2.0 3.0 4.5 6.0
2.0 3.0 4.5 6.0
2.0 3.0 4.5 6.0
2.0 3.0 4.5 6.0
2.0 3.0 4.5 6.0
2.0 3.0 4.5 6.0
2.0 3.0 4.5 6.0
6.0
6.0
3.0 4.5 6.0
2.0 4.5 6.0
- 55 to 25_C
- 55 to 25_C
0.1
0.26 0.26 0.26
200 160 35 30
0.1 0.1 0.1
80 48 28 21
70 40 20 16
90 56 32 25
70 40 20 16
70 40 20 16
10 15 30 50
4
Guaranteed Limit
Guaranteed Limit
v 85_C v 125_C
v 85_C v 125_C
1.0
0.33 0.33 0.33
105 70 38 31
250 185 45 40
0.1 0.1 0.1
9 14 28 45
95 65 32 25
80 45 25 21
80 45 25 21
80 45 25 21
40
MC54/74HC390A
1.0
0.40 0.40 0.40
180 100 45 40
300 210 60 50
160
110 75 40 30
0.1 0.1 0.1
8 12 25 40
90 50 30 27
90 50 30 27
90 50 30 27
MOTOROLA MHz Unit Unit A A ns ns ns ns ns ns V
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NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High-Speed CMOS Data Book (DL129/D). * Used to determine the no-load dynamic power consumption: PD = CPD VCC 2 f + ICC VCC . For load considerations, see Chapter 2 of the Motorola High-Speed CMOS Data Book (DL129/D). NOTES: 1. For propagation delays with loads other than 50 pF, see Chapter 2 of the Motorola High-Speed CMOS Data Book (DL129/D). 2. Information on typical parametric values can be found in Chapter 2 of the Motorola High-Speed CMOS Data Book (DL129/D).
IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I III I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I III I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tf = tf = 6 ns)
MOTOROLA
TIMING REQUIREMENTS (Input tr = tf = 6 ns)
MC54/74HC390A
Symbol
Symbol
tTLH, tTHL
CPD
trec
tf, tf
Cin
tw
tw
Power Dissipation Capacitance (Per Counter)*
Maximum Input Rise and Fall Times (Figure 1)
Minimum Pulse Width, Reset (Figure 2)
Minimum Pulse Width, Clock A, Clock B (Figure 1)
Minimum Recovery Time, Reset Inactive to Clock A or Clock B (Figure 2)
Maximum Input Capacitance
Maximum Output Transition Time, Any Output (Figures 1 and 3)
Parameter
Parameter
4 VCC V VCC V 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 -- - 55 to 25_C - 55 to 25_C 1000 800 500 400 75 27 15 13 75 27 15 13 25 15 5 5 10 75 27 15 13
Typical @ 25C, VCC = 5.0 V
Guaranteed Limit
Guaranteed Limit
v 85_C v 125_C
v 85_C v 125_C
High-Speed CMOS Logic Data DL129 -- Rev 6 1000 800 500 400 95 32 19 15 95 32 19 15 30 20 6 5 10 95 32 19 15 35 1000 800 500 400 110 36 22 19 110 36 22 19 110 36 22 19 40 30 10 7 10 Unit Unit pF pF ns ns ns ns ns
MC54/74HC390A
PIN DESCRIPTIONS
INPUTS Clock A (Pins 1, 15) and Clock B (Pins 4, 15) Clock A is the clock input to the / 2 counter; Clock B is the clock input to the / 5 counter. The internal flip-flops are toggled by high-to-low transitions of the clock input. CONTROL INPUTS Reset (Pins 2, 14) Asynchronous reset. A high at the Reset input prevents counting, resets the internal flip-flops, and forces QA through QD low. OUTPUTS QA (Pins 3, 13) Output of the / 2 counter. QB, QC, QD (Pins 5, 6, 7, 9, 10, 11) Outputs of the / 5 counter. QD is the most significant bit. QA is the least significant bit when the counter is connected for BCD output as in Figure 4. QB is the least significant bit when the counter is operating in the bi-quinary mode as in Figure 5.
SWITCHING WAVEFORMS
tf 90% 50% 10% 10% tw 1/fmax tPLH Q 90% 50% 10% tTLH tTHL CLOCK tPHL Q tr VCC GND RESET tPHL 50% trec 50% GND 50% GND tw VCC
CLOCK
VCC
Figure 1.
Figure 2.
TEST CIRCUIT
TEST POINT OUTPUT DEVICE UNDER TEST
CL*
* Includes all probe and jig capacitance
Figure 3.
High-Speed CMOS Logic Data DL129 -- Rev 6
5
MOTOROLA
MC54/74HC390A
EXPANDED LOGIC DIAGRAM
CLOCK A 1, 15 C D R Q Q 3, 13 QA
CLOCK B
4, 12 D
C R
Q Q 5, 11 QB
C D R
Q Q 6, 10 Q C
C D RESET 2, 14 R Q 7, 9 Q D
TIMING DIAGRAM (QA Connected to Clock B)
0 CLOCK A RESET QA QB QC QD
1
2
3
4
5
6
7
8
9
0
1
2
3
4
5
6
MOTOROLA
6
High-Speed CMOS Logic Data DL129 -- Rev 6
MC54/74HC390A
APPLICATIONS INFORMATION
Each half of the MC54/74HC390A has independent / 2 and / 5 sections (except for the Reset function). The / 2 and / 5 counters can be connected to give BCD or bi-quinary (2-5) count sequences. If Output QA is connected to the Clock B input (Figure 4), a decade divider with BCD output is obtained. The function table for the BCD count sequence is given in Table 1. To obtain a bi-quinary count sequence, the input signals connected to the Clock B input, and output Q D is connected to the Clock A input (Figure 5). QA provides a 50% duty cycle output. The bi-quinary count sequence function table is given in Table 2.
Table 1. BCD Count Sequence*
Output Count 0 1 2 3 4 5 6 7 8 9 QD L L L L L L L L H H QC L L L L H H H H L L QB L L H H L L H H L L QA L H L H L H L H L H
Table 2. Bi-Quinary Count Sequence**
Output Count 0 1 2 3 4 8 9 10 11 12 QA L L L L L H H H H H QD L L L L H L L L L H QC L L H H L L L H H L QB L H L H L L H L H L
* QA connected to Clock B input.
** QD connected to Clock A input.
CONNECTION DIAGRAMS
1, 15 /2 COUNTER 3, 13 QA 1, 15 CLOCK A /2 COUNTER 3, 13 QA
CLOCK A
CLOCK B
4, 12
5, 11 /5 COUNTER 6, 10 7, 9
QB QC QD
CLOCK B
4, 12
/5 COUNTER
5, 11 6, 10 7, 9
QB QC QD
RESET
2, 14
2, 14 RESET
Figure 4. BCD Count
Figure 5. Bi-Quinary Count
High-Speed CMOS Logic Data DL129 -- Rev 6
7
MOTOROLA
MC54/74HC390A
OUTLINE DIMENSIONS
-A -
16 9
J SUFFIX CERAMIC PACKAGE CASE 620-10 ISSUE V
-B - C L
1
8
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 4. DIM F MAY NARROW TO 0.76 (0.030) WHERE THE LEAD ENTERS THE CERAMIC BODY. INCHES MIN MAX 0.750 0.785 0.240 0.295 -- 0.200 0.015 0.020 0.050 BSC 0.055 0.065 0.100 BSC 0.008 0.015 0.125 0.170 0.300 BSC 15 0 0.020 0.040 MILLIMETERS MIN MAX 19.05 19.93 6.10 7.49 -- 5.08 0.39 0.50 1.27 BSC 1.40 1.65 2.54 BSC 0.21 0.38 3.18 4.31 7.62 BSC 15 0 1.01 0.51
-T
SEATING - PLANE
N E F G D 16 PL 0.25 (0.010)
M
K M J 16 PL 0.25 (0.010)
M
TB
S
TA
S
DIM A B C D E F G J K L M N
-A -
16 9
N SUFFIX PLASTIC PACKAGE CASE 648-08 ISSUE R
B
1
8
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. DIM A B C D F G H J K L M S INCHES MILLIMETERS MIN MAX MIN MAX 0.740 0.770 18.80 19.55 6.35 0.250 0.270 6.85 3.69 0.145 0.175 4.44 0.39 0.015 0.021 0.53 1.02 0.040 0.070 1.77 0.100 BSC 2.54 BSC 0.050 BSC 1.27 BSC 0.21 0.008 0.015 0.38 2.80 0.110 0.130 3.30 7.50 0.295 0.305 7.74 0 0 10 10 0.020 0.040 0.51 1.01
F S
C
L
-T - H G D 16 PL 0.25 (0.010)
M
SEATING PLANE
K
J TA
M
M
-A -
16 9
D SUFFIX PLASTIC SOIC PACKAGE CASE 751B-05 ISSUE J
-B -
1 8
P 8 PL 0.25 (0.010)
M
B
M
G F
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. DIM A B C D F G J K M P R MILLIMETERS MIN MAX 9.80 10.00 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0 7 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.386 0.393 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0 7 0.229 0.244 0.010 0.019
K C -T SEATING -
PLANE
R X 45
M D 16 PL 0.25 (0.010)
M
J
T
B
S
A
S
MOTOROLA
8
High-Speed CMOS Logic Data DL129 -- Rev 6
MC54/74HC390A
OUTLINE DIMENSIONS
DT SUFFIX PLASTIC TSSOP PACKAGE CASE 948F-01 ISSUE O
16X K REF
0.10 (0.004) 0.15 (0.006) T U
S
M
TU
S
V
S
K
K1
2X
L/2
16
9
J1 B -U-
L
PIN 1 IDENT. 1 8
SECTION N-N
J
N 0.25 (0.010) 0.15 (0.006) T U
S
A -V- N F DETAIL E
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH. PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-. MILLIMETERS MIN MAX 4.90 5.10 4.30 4.50 --- 1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.18 0.28 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ INCHES MIN MAX 0.193 0.200 0.169 0.177 --- 0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.007 0.011 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_
C 0.10 (0.004) -T- SEATING
PLANE
H D G
DETAIL E
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters can and do vary in different applications. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.
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JAPAN: Nippon Motorola Ltd.; Tatsumi-SPD-JLDC, Toshikatsu Otsuki, 6F Seibu-Butsuryu-Center, 3-14-2 Tatsumi Koto-Ku, Tokyo 135, Japan. 03-3521-8315 HONG KONG: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park, 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852-26629298
High-Speed CMOS Logic Data DL129 -- Rev 6
CODELINE
9
*MC54/74HC390A/D*
EEC CC EEC CC EEC CC EEC CC
M
-W-
DIM A B C D F G H J J1 K K1 L M
MC54/74HC390A/D MOTOROLA

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